1. Field of the Invention
This invention relates to computer data storage systems, and more particularly to disk mirroring techniques in computer data storage systems.
2. Description of the Related Art
A typical computer system includes one or more hard disk drives (i.e., disk drives) for storing data. While the reliabilities of disk drives continue to improve, it is only a matter of time before a given disk drive fails. Data storage systems commonly implement one of several redundant array of inexpensive/independent disks (RAID) techniques in order to allow stored data to remain available despite a failure of one of the disk drives.
RAID level 1, or disk mirroring, stores identical copies of data on two different disk drives. Disk mirroring involves the exact replication of data. A mirrored disk array uses twice as many disks as a non-redundant disk array. Data written to one disk is also written to a redundant disk, such that there are always two physical copies of the same information. When data is read, it can be retrieved from the disk with the shorter queuing, seek, and rotational delays. If a disk drive of a RAID-1 system fails, the other copy is used to service requests and reconstruct a new mirrored disk. Disk mirroring is frequently used in database applications where availability and transaction rates are more important than storage efficiency. Since a block of data needs to be written to two different locations, a write performance penalty may be associated with mirroring.
Intelligent/Integrated drive electronics (IDE) is an interface technology for mass storage devices (e.g., disk drives) wherein the controller is integrated into the drive, and AT Attachment (ATA) is a disk drive interface standard. The two terms and their acronyms are often used interchangeably. Several versions of the ATA standard exist, including the basic ATA standard, Fast ATA, ATA-2, Fast ATA-2, ATA-3, and Ultra ATA. As used herein, the term xe2x80x9cAT attachmentxe2x80x9d and the acronyms xe2x80x9cATAxe2x80x9d and xe2x80x9cIDExe2x80x9d refer to all variants of ATA-type or IDE-type interfaces. The basic ATA standard (ANSI X3.221-1994) supports a single 16-bit parallel data channel which may be shared by two separate devices configured as master and slave.
Today""s disk drive market consists mainly of AT attachment (ATA), small computer systems interface (SCSI) and fibre channel drives. Fibre channel and SCSI drives are employed in enterprise class storage systems, while ATA drives are often limited to desktop applications. At the time of this disclosure, ATA drives are often a factor of between 2 to 3 times cheaper than SCSI drives. The ATA bus is a shared bus between a host and a maximum of 2 ATA drives.
When two ATA drives are connected to an ATA bus, they are popularly referred to as a master/slave pair. Both the master and slave drives include a set of interface registers that provide control and status information. Whenever the host writes to a register, the information is written into the corresponding registers of both the master drive and the slave drive. For example, during ATA operations, the host selects the desired drive by writing 0 (selects master drive) or 1 (selects slave drive) to a drive selection bit in an ATA device/head register. The host then writes a command to an ATA command register. Both the master drive and the slave drive check the device selection bit, and only the selected drive executes the command and responds to the host.
FIG. 1 is a diagram of one embodiment of a typical computer system 10 including a host 12 coupled to two devices 16A-16B via an ATA controller 14 and an ATA bus 18. Devices 16A and 16B include ATA interfaces, and may be ATA storage devices. Examples of ATA storage devices include hard disk drives, compact disk read only memory (CD-ROM) drives, and tape drives. Devices 16A and 16B in FIG. 1 are configured to form a xe2x80x9cmaster/slavexe2x80x9d device pair according to the ATA standards. Either device 16A or device 16B is configured to be a xe2x80x9cmasterxe2x80x9d device, and the other device 16 is configured to be a xe2x80x9cslavexe2x80x9d device. Host 12 accesses devices 16A and 16B via ATA controller 14 and ATA bus 18. The current ATA standards allow one or two devices to be coupled to host 12 via ATA controller 14. It is noted that many computer systems include two ATA controllers, thus allowing up to four devices with ATA interfaces to be coupled to a host.
In the known embodiment of FIG. 1, ATA bus 18 is typically implemented as a flat ribbon cable having multiple conductors with three connectors attached thereto. A first of the three connectors is located at one end of the ribbon cable, and the other two connectors are positioned close together near the other end of the ribbon cable. ATA controller 14 is coupled to the first connector, and devices 16A and 16B are coupled to the other two connectors. ATA bus 18 acts as a xe2x80x9cshared busxe2x80x9d coupling devices 16A and 16B to ATA controller 14.
ATA bus 18 includes a data bus 20, a control bus 22, and a status bus 24. Signal lines of data bus 20 are bidirectional signal lines which convey the ATA data signals between ATA controller 14 and devices 16A and 16B. The ATA data signals include data bus bit 0 (DD0) through DD15. Signal lines of control bus 22 convey the ATA control signals from ATA controller 14 to devices 16A and 16B. The ATA control signals include address signals and other control signals. The address signals include chip select 0 (CS0xe2x88x92), CS1xe2x88x92, device address bit 0 (DA0), DA1, and DA2. (The xe2x80x9cxe2x88x92xe2x80x9d symbol after a signal name indicates that the signal is active low; asserted when the signal is a logic low level and negated or deasserted when the signal is a logic high level.) The other control signals include input/output read (DIORxe2x88x92), input/output write (DIOWxe2x88x92), direct memory access acknowledge (DMACKxe2x88x92), passed diagnostics (PDIAGxe2x88x92), and reset (RESETxe2x88x92).
Signal lines of status bus 24 convey the ATA status signals from device 16A or device 16B to ATA controller 14. The ATA status signals include direct memory access request (DMARQ), interrupt request (INTRQ), and input/output ready (IORDY). As described above, the current ATA standards allow only one of the devices 16A and 16B to be selected at any given time. Only the selected device drives the signal lines of status bus 24. Thus the current ATA standards rule out a situation where both devices 16A and 16B are driving one or more signal lines of status bus 24 at the same time.
In order to preclude a loss of critical data stored via disk drives, it is possible to implement a RAID 1 data storage system in the typical computer system 10 of FIG. 1. In this situation, devices 16A and 16B may form a mirrored pair of disk drives. However, as only one of the mirrored pair of disk drives may be accessed at any given time, a significant amount of time is spent sequentially writing data to one disk drive of the mirrored pair, and then writing the same data to the other disk drive of the mirrored pair. First one ATA drive must be selected and written to, and then the other drive is selected and written to with the same data. It would thus be desirable to have a mechanism for more efficiently mirroring data in storage systems such as ATA systems in which conventionally only one drive on a port may be written to at a time.
A circuit comprising mirroring logic configured to couple to a controller, a first device, and a second device may be provided. Various methods for configuring first and second devices (e.g., data storage devices) to carry out a command from a controller simultaneously, which may be embodied within the mirroring logic, may be provided. A system including the mirroring logic, the controller, and the first and second devices may be provided. The first and second devices may include multiple registers. The mirroring logic may be configured to operate in a first connect mode wherein the mirroring logic allows the registers of the first device to be accessed from the controller and prevents the registers of the second device from being accessed from the controller. The mirroring logic may also be configured to operate in a second connect mode wherein the mirroring logic allows the registers of the second device to be accessed from the controller and prevents the registers of the first device from being accessed. The first and second devices may be configured via the mirroring logic such that the first and second devices are selected simultaneously. When selected simultaneously, the first and second devices may carry out a subsequently issued command simultaneously.
In one embodiment, the registers of the first and second devices may be accessed via multiple control signals produced by the controller. The mirroring logic may be coupled to receive a portion of the control signals and configured to selectively provide the portion of the control signals to the first and second devices. In the first connect mode, the mirroring logic provides the portion of the control signals to only the first device such that the registers of only the first device are accessed. In the second connect mode, the mirroring logic provides the portion of the control signals to only the second device such that the registers of only the second device are accessed.
For example, in some embodiments the first and second devices may include AT Attachment (ATA) interfaces conforming to an ATA standard. In this situation, the control signals include ATA control signals, and the first and second devices are configurable to be selected in response to register accesses via the ATA control signals. The first and second devices carry out received commands only when selected. In one embodiment, when the mirroring logic is in the first connect mode, the mirroring logic provides the ATA address signals to only the first device such that the registers of only the first device are accessed. In the second connect mode, the mirroring logic provides the ATA address signals to only the second device such that the registers of only the second device are accessed.
In an embodiment, the mirroring logic may be coupled to receive a first set of status signals from the first device, and a corresponding second set of status signals from the second device. The mirroring logic may be configured to produce a third set of status signals dependent upon the first and second sets of status signals. The mirroring logic may provide the third set of status signals to the controller.
The mirroring logic may be further configurable to operate in a simultaneous write mode, wherein in the simultaneous write mode the mirroring logic is configured to: (i) provide all of the control signals to both the first and second devices, and (ii) produce the third set of status signals by logically ANDing corresponding status signals of the first and second sets of status signals.
The mirroring logic may be further configurable to operate in a normal mode, wherein in the normal mode the mirroring logic is configured to: (i) provide all of the control signals to both the first and second devices, and (ii) produce the third set of status signals by connecting together corresponding status signals of the first and second sets of status signals.
In general, an embodiment of a system may include the controller, the first and second devices (e.g., data storage devices), and the mirroring logic. As described above, the controller may be configured to produce multiple control signals, and the first and second devices may include multiple registers accessed via the control signals. The mirroring logic may be coupled to the first and second devices and to receive a portion of the control signals. The mirroring logic may be configurable to provide the portion of the control signals to: (i) only the first device in a first mode so that the registers of the second device are not accessed, (ii) only the second device in a second mode so that the registers of the first device are not accessed, and (iii) both the first and second devices in a third mode so that the registers of both the first and second devices are accessed. The mirroring logic may be configured to allow both the first and second devices to be selected simultaneously. The third mode may correspond to a normal mode or a simultaneous write mode.
One embodiment of the system may include a pair of devices (e.g., hard disk drives) each having an ATA interface conforming to an ATA standard, wherein one of the pair of devices is configured as a master device and the other device is configured as a slave device. The mirroring logic may be coupled to the pair of devices and to receive multiple ATA control signals, wherein the ATA control signals include multiple ATA address signals. The mirroring logic is configurable to operate in one of multiple modes comprising: (i) a first connect mode wherein the mirroring logic provides the ATA address signals to only the master device, and (ii) a second connect mode wherein the mirroring logic provides the ATA address signals to only the slave device. The mirroring logic may be configured to allow both the master and slave devices to be selected simultaneously.
The mirroring logic may be configured to enter the first connect mode in response to receiving a first connect mode command (e.g., three consecutive writes to the ATA features register). The mirroring logic may also be configured to enter the second connect mode in response to a second connect mode command (e.g., receiving three consecutive writes to the ATA device/control register).
The mirroring logic may produce a third set of ATA status signals dependent upon a first set of ATA status signals received from the master device and a corresponding second set of status signals received from the slave device. The mirroring logic may provide the third set of status signals to the controller.
In the normal mode, the mirroring logic: (i) provides the ATA address signals to both the master and slave devices, and (ii) produces the third set of ATA status signals by connecting together corresponding ATA status signals of the first and second sets of ATA status signals to behave as in a conventional ATA configuration. The mirroring logic may be configured to enter the normal mode in response to receiving a normal mode command (e.g., three consecutive writes to the ATA cylinder low register).
In the simultaneous write mode, the mirroring logic: (i) provides the ATA address signals to both the master and slave devices, and (ii) produces the third set of ATA status signals by logically ANDing corresponding ATA status signals of the first and second sets of ATA status signals. The mirroring logic may be configured to enter the simultaneous write mode in response to receiving a simultaneous write mode command (e.g., three consecutive writes to the ATA cylinder high register).
In a system comprising a controller (e.g., an ATA controller), a first storage device and a second storage device (e.g., ATA storage devices coupled to the same port of the ATA controller), wherein each of the pair of devices includes multiple registers mapped to the same register address space, a method for configuring the first storage device and the second storage device to carry out a command from the controller simultaneously includes writing to a first register in the address space to select the first storage device to respond to commands. The registers of the first storage device are prevented from being accessed. While the registers of the first storage device are prevented from being accessed, a write operation is directed to the first register in the address space to select the second storage device. As a result, both the first storage device and the second storage device are selected. The registers of both the first storage device and the second storage device are allowed to be accessed. While the registers of both the first and second storage devices are allowed to be accessed, a command is written to a command register in the register address space. The first storage device and the second storage device receive the command and both carry out the command approximately simultaneously.
Where the command is a write command, the method may include determining if the first storage device is ready to receive data, determining if the second storage device is ready to receive data, and performing the following if both the first storage device and the second storage device are ready to receive data: (i) allowing the registers of both the first storage device and the second storage device to be accessed, and (ii) writing a block of data to corresponding data registers of the first storage device and the second storage device, wherein the first storage device and the second storage device store the data approximately simultaneously.
The determining if the first storage device is ready to receive data may include: (i) preventing the registers of the second storage device from being accessed, and (ii) while the registers of the second storage device are prevented from being accessed, reading a value from a status register of the first storage device.
The determining if the second storage device is ready to receive data may include: (i) preventing the registers of the first storage device from being accessed, and (ii) while the registers of the first storage device are prevented from being accessed, reading a value from a status register of the second storage device.